1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device embedded with a power-on reset circuit to initialize internal circuitry when power is turned on.
2. Description of the Background Art
Semiconductor memory devices such as a dynamic random access memory (DRAM) are provided with a power-on reset circuit to initialize the internal latch circuit to prevent erroneous operation at the time of power on.
FIG. 21 is a circuit diagram of a structure of a conventional typical power-on reset circuit 502.
Referring to FIG. 21, power-on reset circuit 502 includes a resistor 504 and a capacitor 506 connected in series between a node to which an external power supply potential extVcc is applied and a ground node, and an inverter 508 having its input connected to the connection node of resistor 504 and capacitor 506 to output a power-on reset signal POR. In FIG. 21, the potential of the connection node of resistor 504 and capacitor 506 is set to a potential VRC.
FIG. 22 is an operation waveform diagram to explain an operation of power-on reset circuit 502.
Referring to FIGS. 21 and 22, power supply potential extVcc begins to rise at time t0 when power is turned on. Since it takes some time to accumulate charge at the electrode of capacitor 506 due to the presence of resistor 504, the rise of potential VRC lags behind the rise of power supply potential extVcc.
The power supply potential is low during time t0 to t1, and the operation of inverter 508 is unstable.
The output of inverter 508 is stable during time t1-t2. Here, inverter 508 provides an output of an H level (logical high) since the level of potential VRC is lower than the level of a threshold voltage VTH of inverter 508. The H level rises as power supply potential extVcc rises. Other internal circuits are reset by a power-on reset signal POR of this level output during time t1-t2. The period of time of t1-t2 is a reset period TRST.
When the level of potential VRC exceeds the level of threshold voltage VTH at time t2, inverter 508 provides an output of an L level (logical low). Therefore, a power-on reset signal POR attains an L level, whereby the reset with respect to internal circuitry is cancelled.
In practice, the internal circuitry in semiconductor devices, particularly in semiconductor memory devices, does not directly receive an external power supply potential to operate. For the purpose of increasing the speed and reducing power consumption, an appropriate internal power supply potential for each of a plurality of embedded internal circuits is generated. The internal circuits receive respective internal power supply potentials to operate. The internal power supply generation circuit generating such internal power supply potential has a large capacitor at the output node to stabilize the internal power supply potential.
Therefore, the rise of the internal power supply potential will lag behind the rise of the external power supply potential. As a result, there is a possibility of the output of the power-on reset circuit being inverted prior to the rise of the internal power supply potential to cancel the power on reset, whereby the internal circuitry may not be initialized sufficiently.
The conventional power-on reset circuit 502 requires an extremely large resistor and capacitor. If a plurality of power-on reset circuits are provided corresponding to each internal power supply potential, the chip area will be increased corresponding to the increase of the power-on reset circuit.
An object of the present invention is to provide a semiconductor device embedded with a power-on reset circuit that operates reliably in response to activation of an internal power supply potential generated in the semiconductor device, and of a small area to realize circuitry.
According to an aspect of the present invention, a semiconductor device includes a first power supply circuit, and a first power-on reset circuit.
The first power supply circuit receives an external power supply potential to generate a first internal power supply potential. The first power-on reset circuit outputs a first reset signal in response to activation of the first internal power supply potential.
The first power-on reset circuit includes a first oscillation circuit, and a first count circuit. The first oscillation circuit oscillates in response to activation of the first internal power supply potential. The first count circuit receives the external power supply potential as an operating power supply potential to count in response to an output of the first oscillation circuit, and causes the first reset signal to make a transition from a reset status to a reset cancel status when the count value reaches a predetermined value.
Since the oscillation circuit oscillates according to the internal power supply potential and the oscillation is counted by the count circuit for generation of a reset signal, the main advantage of the present invention is that an appropriate reset signal can be generated even in the case where the rise of an internal power supply potential is delayed with respect to an external power supply potential.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.